Semiconductor device and manufacturing method thereof

ABSTRACT

A semiconductor device including a first field effect transistor having a source, a first conductivity type drain, a gate, and a first conductivity type channel layer formed beneath the gate and between the source and the drain. The device also includes a first conductivity type well region, a second conductivity type channel layer formed on the surface of the well region, a first wire that connects an end of the second conductivity type channel layer to the first conductivity type drain, a second wire that connects the other end of the second conductivity type channel layer to a power source, and a third wire  208  that connects the first conductivity type well region to the gate of the first field effect transistor. This semiconductor device and manufacturing method thereof enables low power consumption and simple control of threshold voltage values as well as decreases the number of conventional manufacturing processes.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part application of Ser. No.10/239,534, filed Feb. 19, 2003, which is based on PCT InternationalApplication No. PCT/JP02/00249, filed Jan. 16, 2002, which is based onJapanese application no. P2001-014987, filed Jan. 23, 2001.

TECHNICAL FIELD

The present invention relates to a semiconductor device andmanufacturing method thereof, in particular, a semiconductor devicehaving complementary logic gates and manufacturing method thereof.

BACKGROUND OF THE INVENTION

CMOS (Complementary Metal-Oxide Semiconductor) type logic gates arewidely used for silicon integrated circuits, though DCFL (Direct CoupledField-Effect Transistor Logic), which is much simpler in structurecompared to CMOS, is widely used for compound semiconductor integratedcircuits.

In compound semiconductor integrated circuits, in particular, in MMIC.(Monolithic Microwave Integrated Circuit), RF (Radio Frequency) switchcircuits into which logic circuits such as decoder circuits are built,have been put into practical use and DCFL circuits are also being usedin these as well.

Since these MMIC circuits are utilized in portable wireless terminalssuch as cellular telephones, their power consumption is a factor thatinfluences the battery life of the terminals. In order to extend thebattery life and enhance the convenience of the terminal users, lowerpower consumption of terminals has been demanded. Consequently, lowerpower consumption of the above-mentioned logic circuits has become amajor concern.

The basic composition of a DCFL type logic circuit used in theabove-mentioned manner will be described referring to the figures. FIG.6A is a schematic of a DCFL type inverter. FIG. 6B is a cross sectionalview of the DCFL type inverter formed on a GaAs semi-insulatingsubstrate.

In FIG. 6B, the cross section of the upper-layer wire is omitted andonly lines that represent wire are shown for sake of simplicity.

As shown in FIGS. 6A and 6B, a DCFL type logic gate is comprised of twoelements; a pull-down transistor 301 and a pull-up resistor 401. Thepull-down transistor 301 shown in FIG. 6B is an n channel type JFET(Junction Field Effect Transistor) and has an n type channel layer 303formed on the surface of a GaAs substrate 302. This n type channel layer303 is, for example, a layer implanted with Si ions.

Ap type gate layer 304 is formed on this n type channel layer 303. Thisp type gate layer 304 is, for example, a layer diffused with Zn.

In addition, an n type source contact region 305 and n type draincontact region 306, between which the p type gate layer 304 is held, areformed on the surface layer of the n type channel layer 303. Both of then type source contact region 305 and n type drain contact region 306are, for example, layers implanted with Si ions.

An insulating film 307 comprised of, for example, silicon nitride film,is formed on the GaAs substrate 302. Contact holes are opened in theinsulating film 307 on both of the n type source contact region 305 andn type drain contact region 306 and then through these contact holes asource ohmic electrode 308 and drain ohmic electrode 309 are formed onthe n type source contact region 305 and the n type drain contact region306, respectively. The source ohmic electrode 308 and the drain ohmicelectrode 309 are, for example, formed by alloying AuGe/Ni into an ohmicjunction.

A gate wire 310 is formed to connect to the p type gate layer 304 and asource wire 311 is formed to connect to the source ohmic electrode 308.A drain wire 312 is also formed to connect the drain ohmic electrode309. The gate wire 310, source wire 311 and drain wire 312 are allmetallic thin film formed from, for example, three layers of Ti/Pt/Au.

In contrast, the pull-up resistor 401 has an n type conductivity layer402 that is formed on the surface layer of the GaAs substrate 302. The ntype conductivity layer 402 is, for example, a layer implanted with Siions. N type contact regions 403 and 404 are formed on the surface layerof the n type conductivity layer 402. Both of the n type contact regions403 and 404 are, for example, layers implanted with a high concentrationof Si ions.

Contact holes are opened in the insulating film 307 on both the n typecontact regions 403 and 404, and ohmic electrodes 405 and 406 are formedthrough these contact holes on the n type contact regions 403 and 404,respectively. These ohmic electrodes 405 and 406 are, for example,formed by alloying AuGe/Ni into an ohmic junction.

Furthermore, an interlayer insulation film 313 is formed on theinsulating film 307. A metal wire 407 (the drain wire 312) and a metalwire 408 are formed on this interlayer insulation film 313. The metalwires 407 and 408 are respectively connected to the ohmic electrodes 405and 406, through the contact holes formed on the interlayer insulationfilm 313. These metal wires 407 and 408 are, for example, a metallicthin film formed from three layers of Ti/Pt/Au.

The manufacturing procedure of the logic gate shown in FIG. 6 will bedescribed referring to FIGS. 7 and 8.

At first, as shown in FIG. 7A, the n type conductivity layer 402implanted with n type impurity ions through a predetermined ionimplantation mask is formed on a formation region 401A of the pull-upresistor 401 of the GaAs substrate 302 after forming, for example, asilicon nitride film or silicon oxide film on the GaAs substrate 302 asa through film 314 for ion implantation.

Next, as shown in FIG. 7B, the n type channel layer 303 implanted with ntype impurity ions through a predetermined ion implantation mask isformed on a formation region 301A of the pull-down transistor 301 of theGaAs substrate 302. Ion implantation that forms the n type conductivitylayer 402 may also be performed after performing ion implantation thatforms the n type channel layer 303.

As shown in FIG. 7C, n type impurities ions are implanted onto the ntype channel layer 303 and the n type conductivity layer 402 of the GaAssubstrate 302 through a predetermined ion implantation mask torespectively form the n type source contact region 305 and the n typedrain contact region 306 as well as the n type contact regions 403 and404.

As shown in FIG. 7D, the through film 314 is removed and the implantedimpurity ions activated by annealing.

As shown in FIG. 8E, the insulating film 307 of, for example, a siliconnitride film is formed on the GaAs substrate 302.

As shown in FIG. 8F, contact holes are opened in the insulating film 307and then p type impurities are diffused through these contact holes toform the p type gate layer 304.

As shown in FIG. 8G, the gate wire 310 is formed on the p type gatelayer 304.

As shown in FIG. 8H, contact holes are opened in the insulating film 307on the n type source contact region 305, the n type drain contact region306 and the n type contact regions 403 and 404. The source ohmicelectrode 308, the drain ohmic electrode 309 and the ohmic electrodes405 and 406 are formed through these contact holes.

Thereafter, as shown in FIG. 6 b, the interlayer insulation film 313 isformed. Contact holes are opened in the interlayer insulation film 313and the source wire 311, drain wire 312 and the metal wires 407 and 408are formed.

The above-mentioned DCFL type logic gate uses a small number of gateswhen compared to the composition of other gates such as SCFL (SourceCoupled FET Logic). Consequently, the surface area of the substrateoccupied by the gates is small, which is favorable for the highintegration of an integrated circuit. Further, when the pull-downtransistor 301 is off, the static current consumption is held low.Because of this, there is the advantage of low power consumption.

Compared to CMOS however, the power consumption is high. This is due tothe fact that when the pull-down transistor 301 is on, static current isconsumed through the pull-up resistor 401 in the logic gate shown inFIG. 6.

In contrast to this, when the pull-up resistor 401 is replaced with a pchannel type FET 501 as shown in FIG. 9A and B, the static currentconsumption when the pull-down transistor 301 is on can be reduced.Consequently, according to the composition shown in FIG. 9A and B,although the power consumption is still high compared to CMOS, it can bebrought close to the power consumption of CMOS.

FIG. 9A is a schematic of a complementary logic gate that has a pchannel type transistor as the pull-up transistor 501. FIG. 9B is across section thereof. As shown in FIG. 9B, the composition of thepull-down transistor 301 is the same as that in FIG. 6B so a descriptionis omitted.

The pull-up transistor 501 has an n type well region 502 formed by ionimplanting, for example, Si onto the surface layer of the GaAs substrate302. In addition, a p type channel layer 503 is formed by diffusing, forexample, Zn onto the surface layer of the n type well region 502. Evenfurther, an n type gate layer 504 is formed by ion implanting, forexample, Si onto the surface layer of the p type channel layer 503.

A p type source contact region 505 and p type drain contact region 506,between which the n type gate layer 504 is held, are formed on thesurface layer of the p type channel layer 503. Both the p type sourcecontact region 505 and the p type drain contact region 506 are layersformed by diffusing, for example, Zn.

Contact holes are opened in the insulating film 307 on both of the ptype source contact region 505 and the p type drain contact region 506and then through these contact holes a source ohmic electrode 507 anddrain ohmic electrode 508 are formed. Both the source ohmic electrode507 and drain ohmic electrode 508 are, for example, formed by alloyingAuGe/Ni into an ohmic junction.

Further, a gate wire 509 is formed to connect to the n type gate layer504, a source wire 510 is formed to connect to the source ohmicelectrode 507 and a drain wire 511 is formed to connect to the drainohmic electrode 508. The gate wire 509, the source wire 510, and thedrain wire 511 are all comprised of metallic thin film formed from, forexample, three layers of Ti/Pt/Au.

An n type well contact region 512, that contains a high concentration ofn type impurities, is formed on the portion of the surface layer of then type well region 502 other than the p type channel layer 503. An ohmicelectrode 513 is formed on the n type well contact region 512. When asilicon substrate is used in place of the GaAs substrate 302 however, anohmic junction is formed by metal wire on the silicon substrate. Becauseof this, including a high concentration of n type impurities in the ntype well contact region is normally not required.

The procedure to manufacture the logic gate shown in FIG. 9 will bedescribed referring to FIGS. 10 and 11.

In this case, to start, the through film 314 for ion implantation isformed using, for example, a silicon nitride film or silicon oxide film,on the GaAs substrate 302, as shown in FIG. 10A

Then, the n type well region 502 is formed on a formation region 501A ofthe GaAs substrate 302 of this pull-up transistor 501 by ion implantingn type impurities through a predetermined ion implantation mask.

Next, as shown in FIG. 10B, the n type channel layer 303 is formed onthe formation region 301A of the pull-down transistor 301 of the GaAssubstrate 302 by ion implanting n type impurities through apredetermined ion implantation mask.

It is possible to form the above-mentioned n type well region 502 afterforming the n type channel layer 303.

Next, as shown in FIG. 10C, the p type channel layer 503 forms on the ntype well region 502 by ion implanting p type impurities through apredetermined ion implantation mask.

It is possible to form the above-mentioned n type channel layer 303after forming the p type channel layer 503.

Next, as shown in FIG. 10D, the n type source contact region 305 and then type drain contact region 306 are formed on the n type channel layer303 by ion implanting n type impurities through a predetermined ionimplantation mask and the n type well contact region 512 is formed onthe n type well region 502 by ion implanting n type impurities through apredetermined ion implantation mask.

As shown in FIG. 10E, the through film 314 is removed and the implantedimpurity ions are activated by annealing.

As shown in FIG. 11F, the insulating film 307 of, for example, a siliconnitride film is formed on the GaAs substrate 302.

As shown in FIG. 11G, openings are respectively formed on the n typechannel layer 303 between the n type source contact region 305 and the ntype drain contact region 306 as well as on the insulating film 307 ofthe p type channel layer 503. Through these openings p type impuritiesare diffused to form the p type gate layer 304, the p type sourcecontact region 505 and the p type drain contact region 506.

As shown in FIG. 11H, the gate wire 310 is formed on the p type gatelayer 304. Further, the source ohmic electrode 507 and the drain ohmicelectrode 508 are formed on the p type source contact region 505 and thep type drain contact region 506, respectively.

As shown in FIG. 11I, an opening is formed on the insulating film 307between the p type source contact region 505 and the p type draincontact region 506 of the formation region 501A of the p type channellayer 503 of the pull-up transistor 501 and then n type impurities arediffused through this opening to form the n type gate layer 504.

As shown in FIG. 11J, the gate wire 509 is formed on the n type gatelayer 504 and the ohmic electrode 513 is formed on the n type wellcontact region 512. Further, the source ohmic electrode 308 is formed onthe n type source contact region 305 and the drain ohmic electrode 309is formed on the n type drain contact region 306.

Thereafter, as shown in FIG. 9B, the interlayer insulation film 313 isformed. Contact holes are formed on the interlayer insulation film 313to form the source wires 311, 510 and the drain wires 312, 511, and soon.

According to the composition that has a pull-up transistor as describedabove, the power consumption can be reduced compared to the compositionthat has the pull-up resistor shown in FIG. 6 although the process toform a well and a gate layer must be added to the manufacturing process.Therefore, the manufacturing cost of the semiconductor devicesincreases.

In the composition shown in FIG. 9, the p type channel layer 503 isformed by ion implantation of impurities into the n type well region 502formed by ion implantation of impurities, and the n type gate layer 504is also formed by ion implantation of impurities into the p type channellayer 503. Consequently, the impurity concentration of the n type gatelayer 504 fluctuates due to the influence resulted from the condition ofthe plurality of ion implantation processes. Because of this, control ofthe threshold voltage value of the pull-up transistor 501 becomescomparatively difficult, which is a factor in reductions to the yield.Increase in the manufacturing cost due to this type of yield reductionis also a problem.

SUMMARY OF THE INVENTION

In view of the above-described problems, the present invention has theobject of providing a semiconductor device having complementary logicgates, which has lower power consumption and threshold voltage values ofwhich is easily controlled with high precision.

Furthermore, the present invention has the object of providing asemiconductor device manufacturing method in which the above-mentionedsemiconductor devices are provided with fewer manufacturing processes.

The semiconductor device according to the present invention is asemiconductor device in which a first field effect transistor having afirst conductivity type channel is formed on the surface layer of asemiconductor substrate and a second field effect transistor having asecond conductivity type channel is also formed on the surface layer ofthe semiconductor substrate. The first field effect transistor has afirst conductivity type channel layer, a first conductivity type sourceregion formed on one end of the first conductivity type channel layer,and a first conductivity type drain region formed on the other end ofthe first conductivity type channel layer. The first field effecttransistor also has a gate region between the first conductivity typesource region and the first conductivity type drain region.

The second field effect transistor has a first conductivity type wellregion comprised of a gate region separated from the first field effecttransistor, in which a second conductivity type channel layer is formedon the first conductivity type well region.

One end of the second conductivity type channel layer is connected tothe first conductivity type drain region by a first wire and the otherend of the second conductivity type channel layer is connected to afirst power source by a second wire. The first conductivity type wellregion comprised of the gate region is connected by a third wire to athe gate region of the first field effect transistor.

In another implementation the semiconductor device according to thepresent invention is a semiconductor device in which a first fieldeffect transistor having a first conductivity type channel is formed onthe surface layer of a semiconductor substrate and a second junctiontype field effect transistor, having a second conductivity type channelis formed on the surface layer of the semiconductor substrate. The firstfield effect transistor has a first conductivity type channel layer, afirst conductivity type source region formed on one end of the firstconductivity type channel layer, and a first conductivity type drainregion formed on the other end of the first conductivity type channellayer. The first field effect transistor also has a gate region betweenthe first conductivity type source region and the first conductivitytype drain region.

The second junction type field effect transistor has a secondconductivity type channel layer separated from the first field effecttransistor, a second conductivity type source region formed on one endof the conductivity type channel layer, and a second conductivity typedrain region formed on the other end of the second conductivity typechannel layer. In this implementation, the second junction type fieldeffect transistor is formed without a gate region between the secondconductivity type source region and the second conductivity type drainregion.

In this composition as well, one end of the second conductivity typechannel layer is connected to a first conductivity type drain region bya first wire and the other end of the second conductivity type channellayer is connected to a first power source by a second wire.

In addition, a third wire connects the first conductivity type wellregion to the gate region of the first field effect transistor. In eachof the semiconductor devices according to the above-mentionedcompositions, the first field effect transistor may have a firstconductivity type gate layer.

Further, the second field effect transistor may have a composition inwhich a well contact region that has an impurity concentration higherthan the first conductivity type well region is formed separately fromthe second conductivity type channel layer on the first conductivitytype well region comprised of the gate region.

This well contact region is connected by the third wire to the gateregion of the first field effect transistor.

The semiconductor substrate in each of the above-mentioned semiconductordevices according to the present invention can be a compoundsemiconductor substrate of, for example, GaAs.

Furthermore, a manufacturing method of the semiconductor deviceaccording to the present invention is the manufacturing method of thesemiconductor device in which the first field effect transistor havingthe first conductivity type channel and the second field effecttransistor having the second conductivity type channel are formed on thesurface layer of the semiconductor substrate. This manufacturing methodhas the object of manufacturing the above-described semiconductordevices using the processes of: forming the first field effecttransistor, which has the first conductivity type channel, the firstconductivity type source region and the first conductivity type drainregion, onto the surface layer of the semiconductor substrate; formingthe first conductivity type well region comprised of the gate region ofthe second field effect transistor separated from the first field effecttransistor onto the surface layer of the semiconductor substrate;forming the second conductivity type channel layer onto the surfacelayer of the first conductivity type well region; forming a first wirewhich connects one end of the second conductivity type channel layer tothe first conductivity type drain region; forming a second wire whichconnects the other end of the second conductivity type channel layer tothe first power source; and forming a third wire which connects thefirst conductivity type well region to the gate region of the firstfield effect transistor.

Further, in the manufacturing method of the semiconductor deviceaccording to the present invention, the above-mentioned process thatforms the first field effect transistor has the processes of: formingthe first conductivity type channel layer onto the surface layer of thesemiconductor substrate; forming the first conductivity type sourceregion and the first conductivity type drain region onto the surfacelayer of the first conductivity type channel layer; and forming thesecond conductivity type gate layer onto the surface layer of the firstconductivity type channel layer between the first conductivity typesource region and the first conductivity type drain region.

In addition, the manufacturing method of the semiconductor deviceaccording to the present invention enables manufacturing thesemiconductor devices through a process that forms the well contactregion containing first conductivity impurities with a concentrationhigher than the first conductivity type well region onto the surfacelayer of the first conductivity type well region separated from thesecond conductivity type channel layer before forming the third wireafter forming the second conductivity type channel layer.

The semiconductor device according to the present invention has almostno static current consumption flow during a low level output andachieves a low power consumption complementary logic gate.

According to the semiconductor device of the present invention, sincethe second field effect transistor causes the first conductivity typewell region to function as a gate and to control the current flow in thesecond conductivity type channel layer, the number of ion implantationprocesses which determine the impurity concentration of the gate can bereduced compared to a case where a gate semiconductor layer is formedonto the surface layer of a channel layer as in, for example, theconventional structure shown in FIG. 9B.

Consequently, controlling threshold voltage values becomes easier.

According to the manufacturing method of the present invention, since itis possible to form a complementary logic gate while avoiding a processin which a gate layer is formed by implanting ions onto the surfacelayer of the second conductivity type channel as in a conventionalmanufacturing method, the number of manufacturing processes can bereduced.

Since the number of ion implantation processes which influence thethreshold voltage value is reduced, it becomes easier to controlthreshold voltage values with higher accuracy.

Further, according to the above-described advantage, the occurrence ofinferior products due to the threshold voltage value decreases, therebyimproving the yield of the semiconductor devices.

Even further, reducing the number of manufacturing processes andimproving the yield make it possible to reduce manufacturing costs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic of the semiconductor device of the presentinvention;

FIG. 1B is a cross sectional view corresponding to FIG. 1A;

FIG. 2 is a diagram showing the transfer characteristics of thecomplementary logic gates of the semiconductor device according to thepresent invention;

FIGS. 3A to 3C are cross sectional views showing the operation of thecomplementary logic gates of the semiconductor device according to thepresent invention;

FIGS. 4A to 4E are cross sectional views showing the manufacturingprocesses of the manufacturing method of the semiconductor deviceaccording to the present invention;

FIGS. 5F to 5J are cross sectional views showing the manufacturingprocesses of the manufacturing method of the semiconductor device of thepresent invention;

FIG. 6A is a schematic of a conventional semiconductor device;

FIG. 6B is a cross sectional view corresponding to FIG. 6A;

FIGS. 7A to 7D are cross sectional views showing the manufacturingrocesses of the manufacturing method of a conventional semiconductordevice;

FIGS. 8E to 8H are cross sectional views showing the manufacturingprocesses of the manufacturing method of a conventional semiconductordevice;

FIG. 9A is a schematic of a conventional semiconductor device;

FIG. 9B is a cross sectional view corresponding to FIG. 9A;

FIGS. 10A to 10E are cross sectional views showing the manufacturingprocesses of the manufacturing method of a conventional semiconductordevice; and

FIGS. 11F to 11J are cross sectional views showing the manufacturingprocesses of the manufacturing method of a conventional semiconductordevice.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

An embodiment of the semiconductor device according to the presentinvention and manufacturing method thereof will be described referringto the attached drawings.

FIG. 1A is a schematic showing a DCFL inverter according to anembodiment of the present invention and FIG. 1B is a cross sectionalview of the DCFL inverter according to the embodiment.

In FIG. 1B, for sake of simplicity, the cross section for the upperlayer wire is omitted and only the lines representing the wires areshown.

As shown in FIGS. 1A and B, the DCFL type logic gate is comprised of twoelements; a pull-down transistor 101 formed of a first field effecttransistor having a first conductivity type channel, such as an n typechannel and a pull-up transistor 201 formed of the second field effecttransistor having a second conductivity type channel, such as a p typechannel.

The pull-down transistor 101 shown in FIG. 1B is a junction type fieldeffect transistor JFET of an n channel type. Further, the pull-uptransistor 201 is effectively a junction type field effect transistorJFET of a p channel type, which causes the first conductivity type, inthis example, an n type well region 202 to function as a gate and tocontrol the p channel.

The pull-down transistor 101 has an n type channel layer 103 of thefirst conductivity type formed on the surface layer of a semiconductorsubstrate 102 comprised of, for example, a GaAs substrate. This n typechannel layer 103 is, for example, a layer implanted with Si ions. A ptype gate layer 104 of the second conductivity type is formed on thesurface layer of the n type channel layer 103. The p type gate layer 104is, for example, a layer diffused with Zn.

An n type drain contact region 106 of the first conductivity type andsimilarly an n type source contact region 105 of the first conductivitytype, between which the p type gate layer 104 is held, are formed on thesurface layer of the n type channel layer 103. The n type source contactregion 105 and drain contact region 106 are, for example, layersimplanted with a high concentration of Si ions.

An insulating film 107 of, for example, silicon nitride film, is formedon the GaAs substrate 102. Contact holes are opened in the insulatingfilm 107 on both of the n type source contact region 105 and the draincontact region 106, and then through these contact holes a source ohmicelectrode 108 and drain ohmic electrode 109 are formed on the n typesource contact region 105 and the drain contact region 106,respectively. The source ohmic electrode 108 and the drain ohmicelectrode 109 are, for example, formed by alloying AuGe/Ni into an ohmicjunction.

A gate wire 110 is formed to connect to the p type gate layer 104, and asource wire 11 is formed to connect to the source ohmic electrode 108. Adrain wire 112 is also formed to connect to the drain ohmic electrode109. The gate wire 110, source wire 111 and drain wire 112 are, forexample, metallic thin films formed from three layers of Ti/Pt/Au.

In contrast, the pull-up transistor 201 has the n type well region 202implanted with, for example, Si ions onto the surface layer of the GaAssemiconductor substrate 102. A p type channel layer 203 of the secondconductivity type is formed onto the surface layer of the n type wellregion 202 of the first conductivity type. This p type channel layer 203is a layer implanted with, for example, Mg, C or Zn ions. Ohmic contactregions 204 and 205 are formed on the surface layer of the p typechannel layer 203. These regions 204 and 205 are implanted with a highconcentration of, for example, Mg, C or Zn of the p type, namely, secondconductivity type.

Contact holes are opened in the insulating film 107 on the p type ohmiccontact regions 204 and 205, and ohmic electrodes 206 and 207 are formedthrough these contact holes. The ohmic electrodes 206 and 207 arecomprised of a metallic thin film formed of, for example, three layersof Ti/Pt/Au.

An interlayer insulation film 113 is formed on the insulating film 107.The ohmic electrode 206 on the output V_(OUT) side is connected to thefirst wire, formed of the drain wire 112 of the pull-down transistor101. A second wire is formed of a power source wire 208 (V_(DD)electrode) to connect to the ohmic electrode 207 on the power sourceV_(DD) side. The electrode wire 208 is comprised of a metallic thin filmformed of, for example, three layers of Ti/Pt/Au similarly to the sourcewire 111 and drain wire 112 of the pull-down transistor 101.

Further, an n type well contact region 209 containing a highconcentration of n type impurities of the first conductivity type, isformed on the surface layer of the n type well region 202 of the portionother than the p type channel layer 203. An ohmic electrode 210 isformed on this well contact region 209. The ohmic electrode 210 isformed by, for example, alloying AuGe/Ni to form an ohmic junction. Athird wire 212 is formed on the surface of the ohmic electrode 210 andconnected to the gate wire 110 (e.g., the gate region) of the pull-downtransistor 101 (e.g., the first field effect transistor).

Next, the operation of the semiconductor device according to theembodiment of the present invention will be described referring to FIGS.2 and 3.

FIG. 2 is a curved line showing the transfer characteristics between thepull-down transistor 101 and the pull-up transistor 201.

FIGS. 3A to 3C are cross sectional views showing typical expansion ofthe depletion layer at points A to C of FIG. 2.

The input V_(IN) at point A in FIG. 2 is a low level. Consequently, thepull-down transistor 101 (n channel type JFET) is off and a high levelvoltage is output to the output V_(OUT). At this time, V_(OUT) of thepull-up transistor 201 (p channel type JFET) is approximately the powersource voltage V_(DD). Therefore, as shown in FIG. 3A, the pn junctionbetween the n type well region 202 and the p type channel layer 203 isat an approximate zero bias from the V_(DD) side to the V_(OUT) side(the pull-down transistor 101 side). This brings the conductance of thep type channel layer 203 up to its maximum value.

V_(IN) at point B in FIG. 2 moves to the center position between a highand low level. At this time, V_(OUT) changes to a voltage lower thanV_(DD) in response to the conductance ratio between the n channel typeJFET 101 and the p channel type JFET 201. As shown in FIG. 3B, becauseof this, a reverse bias of the amount “V_(DD)−V_(OUT)” is applied to theV_(OUT) side of the p type channel layer 203 with respect to the n typewell region 202, thereby reducing the conductance.

V_(IN) at point C in FIG. 2 changes to a high level and the n channeltype JFET 101 turns on. This brings V_(OUT) close to a low level. Atthis time, as shown in FIG. 3C, the end of the V_(OUT) side of the ptype channel layer 203 is reverse biased by the voltage V_(DD) withrespect to the n type well region 202. Consequently, the p channel islost from the n type well region 202 due to the depletion layer togreatly reduce the conductance. As a result, there is almost no flow ofstatic power consumption during a low level output, thereby achieving alow power consumption complementary logic gate. This type of the lowpower consumption complementary logic gate is ideally applied toportable wireless terminals such as an MMIC.

Next, an embodiment of the manufacturing method of the above-mentionedembodiment of the semiconductor device according to the presentinvention will be described referring to the process diagrams of FIGS. 4and 5.

At first, as shown in FIG. 4A, a silicon nitride film or silicon oxidefilm, for example, is formed on the GaAs semiconductor substrate 102 asa through film 114 for ion implantation. The through film 114 comprisedof a silicon nitride film can be formed by a plasma CVD whose ingredientgas is, for example, SiH4 and N2.

The through film 114 is provided for the purpose of preventing damage tothe substrate due to ion implantation. Consequently, the film thicknessof the through film 114 is determined by taking into consideration therequired energy of the ion implantation in order to obtain the desiredFET characteristics. When forming a silicon nitride film as the throughfilm 114, the film thickness can be, for example, 50 nm.

Next, as shown in FIG. 4B, in order to form the n type well region 202,n type impurities, for example Si ions, are implanted through apredetermined ion implantation mask in the formation region 201A of thepull-up transistor 201 of the GaAs semiconductor substrate 102.

Next, as shown in FIG. 4C, in order to form the n type channel layer103, n type impurity ions are implanted through a predetermined ionimplantation mask in the formation region 101A of the pull-downtransistor 101 of the GaAs semiconductor substrate 102.

After the ion implantation to form the n type channel layer 103, the ionimplantation to form the n type well region 202 can also be performed.Si, for example, is used as the n type impurity. The impurity profile ofthe n type channel layer 103 is determined in response to the desiredcharacteristics of the n channel type JFET 101.

Next, as shown in FIG. 4D, p type impurity ions are implanted through apredetermined ion implantation mask in the formation region 201A of then type well region 202 of the pull-up transistor 201 in order to formthe p type channel layer 203. It is possible to perform the ionimplantation to form the n type channel layer 103 after the ionimplantation to form the p type channel layer 203.

The impurity profile of the n type well region 202 and the p typechannel layer 203 of the pull-up transistor 201 are determined such thatthe V_(OUT) terminal side of the p type channel layer 203 is depleted toenter a pinch-off state by reverse bias between the n type well region202 when the logic gate shown in FIG. 1 outputs a low level voltage.

The concentration of the n type well region 202 is preferably set to theconcentration higher than the sum total of the concentration of theshallow acceptor level and deep acceptor level existing in the GaAssubstrate 102 to reduce the influence that incurs the pinchoff voltageof the p type channel due to the depletion from the substrate side.

Next, as shown in FIG. 4E, n type impurity ions are implanted into theGaAs substrate 102 in order to form the n type source contact region105, the n type drain contact region 106 and the n type well contactregion 209. The impurity profile of the n type source contact region 105and the n type drain contact region 106 are determined in response tothe desired characteristics of the n channel type JFET 101. For example,Si ions are implanted as the impurity with ion energy of 150 KeV and adoping amount of 2×10¹³ ions/cm². The n type well contact region 209 canbe formed simultaneously with the n type source contact region 105 andthe n type drain contact region 106.

Next, as shown in FIG. 5F, the through film 114 is removed using, forexample, a hydrofluoric acid (HF) type etching solution and theimplanted impurity ions are activated by annealing. The annealingtemperature is preferably from 800° C. to 850° C. In order to preventarsenic (As) from vaporizing and escaping from the GaAs substrate 102during this annealing, arsine is supplied to have a predeterminedpartial pressure.

As shown in FIG. 5G, the insulating film 107, which is comprised of, forexample, a silicon nitride film with a thickness of 300 nm, is formed onthe GaAs substrate 102. The insulating film 107 comprised of thissilicon nitride film can be formed by a plasma CVD whose ingredient gasis, for example, SiH₄ and N₂.

As shown in FIG. 5H, openings are formed on the insulating film 107.These openings are provided on the formation region of the p type gatelayer 104 of the pull-down transistor 101 and the each formation regionof the p type ohmic contact regions 204 and 205 of the pull-uptransistor 201. The formation of the openings can be performed by meansof anisotropic etching such as reactive ion etching (RIE) through anetching mask of a predetermined pattern. A mixture such as CF₄ and H₂ isused for the RIE etching gas.

In this manner, p type impurities of the second conductivity type arediffused through the openings provided on the insulating film 107 toform the p type gate layer 104, namely, the p type gate layer on thepull-down transistor 101 as well as to form the p type ohmic contactregions 204 and 205 on the p type channel layer 203 of the pull-uptransistor 201.

Hereupon, Zn is ideally used as the p type impurity. Diethyl zinc gas isused as the Zn diffusion source and Zn is diffused onto the substrateby, for example, an open tube vapor-phase diffusion method. Arsine isadded until a predetermined partial pressure in order to prevent arsenicfrom escaping from the substrate due to heating during Zn diffusion. Theheating temperature during the Zn diffusion is preferably about 600° C.

Next, as shown in FIG. 51, the gate wire 110 and the ohmic wires 206 and207 are formed. The gate wire 110 forms an ohmic junction with respectto the p type gate layer 104. The ohmic wires 206 and 207 form ohmicjunctions with respect to the p type ohmic contact regions 204 and 205,respectively.

In order to form the gate wire 110 and the ohmic wires 206 and 207, atfirst, a metallic thin film comprised of electrode material, is allowedto accumulate on the entire surface of the insulating film 107 includingthe inside of the openings. The electrode material is for example, athree-layer film of Ti/Pt/Au and the film thickness is, for example, 30nm for the Ti layer, 50 nm for the Pt layer and 200 nm for the Au layer.These metallic thin films can be formed using, for example, electronbeam deposition or sputtering.

Next, a photoresist layer is formed on this metallic thin film. Then, anetching mask is formed by exposing and developing a predeterminedpattern, in other words using photolithographic technology and themetallic thin film is etched through the openings of this etching mask.The etching can be performed by, for example, RIE or ion milling.Thereafter, the resist is removed.

Next, as shown in FIG. 5J, the source ohmic electrode 108 and drainohmic electrode 109 of the pull-down transistor 101 as well as the ohmicelectrode 210 of the pull-up transistor 201 are formed. In order to formthese three ohmic electrodes 108, 109 and 210, at first, contact holesare opened on portions, in which these ohmic electrodes are formed, ofthe insulating film 107. The formation of these contact holes can beperformed by means of anisotropic etching such as RIE through theopenings of the etching mask which is formed by the photoresist. Amixture such as CF₄ and O₂ is used for the RIE etching gas.

Next, the metallic thin film, comprised of the electrode material, isallowed to accumulate onto the entire surface while the resist of theetching mask is left as is. A two-layer film of, for example AuGe alloyand nickel is used for the electrode material. The film thickness is,for example, 170 nm for the AuGe layer and 40 nm for the Ni layer. Thesemetallic thin films can be formed using, for example, ohmic-resistanceheating vapor deposition.

Thereafter, the semiconductor substrate is soaked in an acetone orresist exfoliation solution to remove by lifting-off any unnecessarymetallic thin film formed on the resist. Heat treatment is alsoperformed in foaming gas. Consequently, an alloyed ohmic junction isformed between the metallic thin film comprised of the two layers ofAuGe alloy and Ni and the contact region of the substrate. The heattreatment for the alloying should be approximately 60 seconds at 450° C.

Next, as shown in FIG. 1B, the source wire 111 and drain wire 112 of thepull-down transistor 101 as well as the power source wire 208 and thethird wire 212 of the pull-up transistor 201 are formed. In order toform these metallic wires, at first, the interlayer insulation film 113that covers the entire surface of the substrate is formed. A siliconnitride film or a silicon oxide film is preferably used for theinterlayer insulation film 113. The interlayer insulation film 113comprised of the silicon nitride film can be formed by a plasma CVDusing a mixture of, for example, SiH₄ and NH₃ as ingredient gas. Thefilm thickness of the interlayer insulation film 113 is, for example,100 nm.

Further, contact holes in the interlayer insulation film 113 are formedon the p type gate layer 104 of the pull-down transistor 101, on thesource ohmic electrode 108, on the drain ohmic electrode 109 and on theohmic electrodes 206, 207, 210 of the pull-up transistor 201. Theformation of these contact holes can be performed by, for example, RIEsimilar to the process that provides the openings on the insulating film107 described in FIG. 5H.

Thereafter, a metallic thin film is formed on the entire surface of theinterlayer insulation film 113 including the inside of the contactholes. The metallic thin film is processed in a wire pattern by, forexample, RIE similar to the process described in FIG. 51. The metallicthin film is a, for example, three-layer film of Ti/Pt/Au and the filmthickness is, for example, 50 nm for the Ti layer, 50 nm for the Ptlayer and 600 nm for the Au layer.

In this manner, the principal elements of the complementary logic gateaccording to the present invention are completed.

According to the embodiment of the manufacturing method of thesemiconductor device of the present invention described above, acomplementary logic gate can be formed without implanting ions onto thesurface layer of a channel layer of a pull-up transistor to form a gatelayer as in a conventional manufacturing method. Because of this, thenumber of manufacturing processes is reduced.

Furthermore, since the number of ion implantation processes whichinfluence the threshold voltage value is reduced, it is easier tocontrol the threshold voltage value. This decreases the occurrence offaulty parts caused by the threshold voltage value, thereby improvingthe yield of the semiconductor devices. Accordingly, reducing the numberof manufacturing processes and improving the yield makes it possible toreduce manufacturing costs.

The embodiments of the semiconductor device and manufacturing methodthereof of the present invention are not limited to the examplesdescribed above. For example, the present invention can also be appliedwhen the first conductivity type is a p type and the second conductivitytype is an n type.

Various modified embodiments of the present invention are also possiblewithout departing from the spirit and scope thereof.

As described above, according to the semiconductor device of the presentinvention, a complementary logic gate with reduced power consumption isdesigned with simpler high-precision control on threshold voltagevalues.

Further, according to the manufacturing method of the semiconductordevice of the present invention, a semiconductor device with low powerconsumption and simpler high-precision control on threshold voltagevalues can be formed in a fewer manufacturing processes.

1. A semiconductor device in which a first field effect transistor having a first conductivity type channel and a second field effect transistor having a second conductivity type channel are formed on a surface layer of a semiconductor substrate, characterized in that: said first field effect transistor has a first conductivity type channel layer, a first conductivity type source region formed on one end of said first conductivity type channel layer, a first conductivity type drain region formed on the other end of said first conductivity type channel layer, and a gate region formed between said first conductivity type source region and first conductivity type drain region, said second field effect transistor has a first conductivity type well region comprised of a gate region separated from said first field effect transistor and a second conductivity type channel layer in said first conductivity type well region; a second conductivity type source region formed on one end of said second conductivity type channel layer and a second conductivity type drain region formed on the other end of said second conductivity type channel layer, a first wire connects one end of said second conductivity type channel layer to said first conductivity type drain region, a second wire connects the other end of said second conductivity type channel layer to a first power source, a third wire connects said first conductivity type well region to said gate region of said first field effect transistor.
 2. A semiconductor device according to claim 1, wherein said gate region of said first field effect transistor is comprised of a first conductivity type gate layer.
 3. A semiconductor device according to claim 2, wherein a well contact region having an impurity concentration higher than said first conductivity type well region is formed on said first conductivity type well region comprised of said gate region of said second field effect transistor separated from said second conductivity type channel layer, a third wire connects said well contact region to said gate region of said first field effect transistor.
 4. A semiconductor device according to claim 1, wherein a well contact region having an impurity concentration higher than said first conductivity type well region is formed on said first conductivity type well region comprised of said gate region of said second field effect transistor separated from said second conductivity type channel layer, a third wire connects said well contact region to said gate region of said first field effect transitor.
 5. A semiconductor device according to claim 1, wherein said semiconductor substrate is a compound semiconductor substrate.
 6. A semiconductor device in which a first field effect transistor having a first conductivity type channel and a second junction type field effect transistor having a second conductivity type channel are formed on the surface layer of a semiconductor substrate, characterized in that: said first field effect transistor has a first conductivity type channel layer, a first conductivity type source region formed on one end of said first conductivity type channel layer, a first conductivity type drain region formed on the other end of said first conductivity type channel layer, and a gate region formed between said first conductivity type source region and said first conductivity type drain region; said second junction type field effect transistor has a second conductivity type channel layer separated from said first field effect transistor, a second conductivity type source region formed on one end of said second conductivity type channel layer, and a second conductivity type drain region formed the other end of said second conductivity type channel layer, wherein a gate region is not provided between the second conductivity type source region and second conductivity type drain region on said second conductivity type channel layer. a first wire connects one end of said second conductivity type channel layer to said first conductivity type drain region. a second wire connects the other end of said second conductivity type channel layer to a first power source. a third wire connects said first conductivity type well region to said gate region of said first field effect transistor.
 7. A semiconductor device according to claim 6, wherein said gate region of said first field effect transistor is comprised of a first conductivity type gate layer.
 8. A semiconductor device according to claim 6, wherein said semiconductor substrate is a compound semiconductor substrate.
 9. A manufacturing method of a semiconductor device in which a first field effect transistor having a first conductivity type channel and a second field effect transistor having a second conductivity type channel are formed on the surface layer of a semiconductor substrate, comprising the processes of: forming a first field effect transistor having a first conductivity type channel, a first conductivity type source region and a first conductivity type drain region, onto the surface layer of said semiconductor substrate; forming a first conductivity type well region comprised of a gate region of said second field effect transistor, onto the surface layer of said semiconductor substrate separated from said first field effect transistor; forming a second conductivity type channel layer onto the surface layer of said first conductivity type well region; forming a first wire which connects one end of said second conductivity type channel layer to said first conductivity type drain region; forming a second wire which connects the other end of said second conductivity type channel layer to a first power source; and forming a third wire which connects said first conductivity type well region to said gate region of said first field effect transistor.
 10. A manufacturing method of the semiconductor device according to claim 9, wherein the process in which said first field effect transistor is formed comprises the processes of: forming a first conductivity type channel layer onto the surface layer of said semiconductor substrate; forming said first conductivity type source region and said first conductivity type drain region onto the surface layer of said first conductivity type channel layer; and forming a second conductivity type gate layer onto the surface layer of said first conductivity type channel layer between said first conductivity type source region and said first conductivity type drain region.
 11. A manufacturing method of the semiconductor device according to claim 9, further comprising: a process that forms a well contact region containing first conductivity type impurities with a concentration higher than said first conductivity type well region onto the surface layer of said first conductivity type well region separated from said second conductivity type channel layer before forming said third wire after forming said second conductivity type channel layer. 